Semiconductor memory devices use a metal line in parallel with a polycrystalline silicon wordline to reduce parasitic delay associated with wordline operation. Periodically across the memory array, contacts are made between the metal line and the associated polycrystalline silicon wordline. Because the metal line has a much lower resistivity than the polycrystalline silicon, a time constant for switching the wordline between high and low logic levels is reduced. Thus data reading and writing operations can be run at a faster rate.
As the density of memory devices increases from generation to generation, the trend is to reduce dimensions of the layout rules for cells faster than the reduction of dimensions in peripheral circuits. In a dynamic random access memory (DRAM), the cell structure is being fabricated above the surface of the silicon substrate. This raised cell structure results in an array that is higher above the substrate surface than peripheral circuits of the device. Such a height differential increases the depth of focus (DOF) required by photolithographic equipment, which must also satisfy reduced array geometry and spacing requirements.
In the manufacturing process, the size and the density of particles are major causes of device failures. The ability to reduce the size and the number of particles lags significantly behind the rate of reduction in pitch between lines included in a device.
A problem that arises while designing a memory array is that reduced pitch between lines creates an environment where particles of a size which historically did not cause defects now do cause defects, such as short circuits between adjacent metal lines running along parallel paths.